Program DS1867.BS2.

' DS1867.BS2
'
' Illustrates an interface with the BASIC Stamp 2
'
'	BASIC Stamp	 		 DS1867
'
'	P0, term 5 ----------------> (/RST), term 5
'	P1, term 6 ----------------> (CLK), term 6	
'	P2, term 7 ----------------> (DQ), term 8
'
' copyright, Towanda Malone, Baltimore, Sept, '98
'

STACK	VAR BYTE
R_POT_1 VAR BYTE
R_POT_0	VAR BYTE

O_BYTE	VAR BYTE
N	VAR BYTE

	DIRS = $00  	        ' all inputs       

	
MAIN:
	STACK = 0		' dummy up some values	
	R_POT_1 = $B0
	R_POT_0 = $40
		
	GOSUB WRITE_VAL

DONE:	GOTO DONE

WRITE_VAL:
SSTART:
	
	DIR0 = 1		' make /RST, CLK and DQ outputs
	DIR1 = 1
	DIR2 = 1

	OUT1 = 0		' CLK low		
	OUT0 = 1		' /RST high

OUT_STACK:
	OUT0 = STACK.BIT0	' output the Stack bit
	GOSUB CLOCK_PULSE

OUT_R_POT_1:	
	O_BYTE = R_POT_1
	GOSUB OUT_BYTE

OUT_R_POT_0:
	O_BYTE = R_POT_0
	GOSUB OUT_BYTE

SSTOP:
	OUT0 = 0		' bring /RST low
	RETURN
		
OUT_BYTE:		' output 8 bits, beginning with most sig bit
	FOR N = 0 TO 7
	   OUT2 = O_BYTE.BIT7
	   GOSUB CLOCK_PULSE
           O_BYTE = O_BYTE * 2	' shift one place to the left
	NEXT	
	RETURN

CLOCK_PULSE:			' bring CLK high and low
	OUT1=1
	OUT1=0
	RETURN

EEPROM.

The 17 bits of wiper position data are not saved to EEPROM unless power is lost. A minimum of 4 ms between 4.5 and 3.0 VDC is required on power down. This can easily be achieved with a 0.1 uFd capacitor across the power terminals V_CC and GRD.

On power up, the data is automatically read from EEPROM. Note that during the power up recovery (a maximum of 10 msec) the pots are set to mid scale (80 hex).

Both the writing to and reading from EEPROM are transparent to the user.

The EEPROM "wear out" is specified at 50,000 writes.

Cascading.

Any number of DS1867 devices may be daisy chained on the same three wire bus, with /RST and CLK multipled to each device and C_OUT of the first DS1867 connected to DQ of the second and C_OUT of the second to DQ of the third, etc. This is simply a shift register.

For three devices where Device #3 is furthest from the processor;

	/RST high
	Stack_3, Pot_1_3, Pot_0_3, 
	Stack_2, Pot_1_2, Pot_0_2,
	Stack_1, Pot_1_0, Pot_0_1,
	/RST low

Note that in this case, 17 X 3 or 51 bits are sent.

Reading the Pot Settings.

The C_OUT terminal may also be used to read the content of a potentiometer. Figure #5 in the data sheet illustrates how C_OUT may be looped back to DQ through a series limiting resistor.

A technique for reading the pot;

Configure processor terminal DQ as an input. /RST high

Note that C_OUT now may be read. A clock pulse causes the state on C_OUT to be loaded into the DQ input on the first DS1867.

This "read and clock" sequence is repeated 17 (or 34 or 51) times and all bits are then back in their previous positions. Bringing /RST low again engages the wipers.

Voltage Swing.

Logic levels associated with the DS1867 are TTL levels; V_CC and ground. An additional terminal, V_B is provided to bias the substrate such that signals on the potentiometer can range from V_B to V_CC. For example, if V_B is tied to -5.0 VDC, the potentials on the pot may swing from -5.0 to 5.0 V.

Timing.

It is worthy of note that the device may be clocked at anything from near DC to 10 MHz. Each pot setting requires 17 clock cycles and thus the resistance may be varied quite quickly.

This raises the possibility of using the DS1867 in real time feedback control applications. In fact, it might be used as a dual 8-bit digital to analog converter.

Again, note that the EEPROM write is performed only on power down, not on each write to the device. Thus, I assume the resistance could be changed some 500,000 times per second indefinitely.

However, I did not note this capability until we had completed testing and the fixture has since been taken down. Thus, this is somewhat speculative. I would be interested if anyone walks down this road.