Interfacing with a Dallas DS1867 Dual
copyright, Towanda Malone and Peter H. Anderson
Baltimore, MD 21239, Sept 98
The focus of this discussion is the DS1867 Dual Potentiometer. The
DS1867 is available in 10K, 50K and 100K models. We sell the DS1867-010
(10K) in a DIP package. A data sheet is available from
The interesting feature of this device is the potentiometer settings
are stored in EEPROM on
power down. These values are then loaded from EEPROM on power up.
In many applications involving data acquisition, an amplifier is
required to buffer a high
impedance sensor and provide gain or attenuation. Accurate sources of
V_ref can be expensive
and all and all the use of a potentiometer is tempting.
I designed circuits for Bell Labs for 20 years and designing a
potentiometer into a circuit was to
be avoided at all costs. The reasons were adjustment was an additional
manufacturing step, the
end user or dissatisfied employees could wreak havoc in toying with the
adjustments, the wiper
was subject to contamination over time, pots used a relatively large
amount of board space and
were relatively expensive.
However, devices such as the DS1867 take away many of those arguments
and permit the
designer to design relatively inexpensive analog circuitry and rely on a
DS1867 to "mop" up the
inaccuracies. The calibration may be no more than a worker or the end
user depressing an up or
down pushbutton while watching an LED flash slower and slower and stopping
when it is at
minimum speed. That is, the craft doesn't need a screw driver and
voltmeter. Rather, the clever
designer can design all of the test instrumentation into the processor.
Note that the resistance associated with the wiper itself is in the
range of 400 to 1K Ohms and
clearly this must be taken into account in designing the interfacing
analog conditioning circuitry.
Note that when used in an op amp configured as a voltage follower, this
R_W is simply in series
with an op amp input and as the input impedance of the op amp is very high
and thus the input
current very low, this wiper resistance is of no significance. In other
configurations, the variation
in wiper resistance might be masked by a much higher series resistance.
The Dallas data sheet
provides a few examples.
The following programs for the BASIC Stamp and PIC illustrate the
interface. Note that in these
programs, the values of the two potentiometers are set in the program.
Clearly, in an actual
application, there would be a mechanism for varying these values.
The two potentiometers consist of terminals H0, L0 and W0 for one pot
and H1, L1 and W1 for
the other. In addition, there is a "stack bit" that permits the selection
of either W0 or W1 to be
gated to output S_OUT. (Dallas doesn't miss a trick).
Potentiometer settings are in the range of 00 - FF (hex). Zero (hex)
corresponds to the wiper
being on the L side, FF (hex) on the H side. Thus, 40 (hex) would cause
the wiper to be
one-quarter of the way between L and H. Note that for a 10K pot, the 256
to a resistor quantizing value of nominally 50 Ohms.
In transferring data to the DS1867, /RST is brought high with clock at
Data is then sent; the stack bit is sent first, followed by the 8-bit
setting of POT 1 (most
significant bit first), followed by the 8-bit setting of POT 0 (most
significant bit first). Thus, a
total of 17 bits are sent.
Each bit is sent by bringing DQ to the appropriate state and then
clocking. Data is clocked into
the DS1867 on the rising edge of the clock pulse.
The /RST lead is then brought low. Only at that time is the new wiper
(It is critical to note that there are only 17 positive going clock
pulses. Towanda spent quite a bit
of time debugging her program and the problem was traced to an erroneous
18 th positive edge at
the end of the sequence.)
; DS1867.ASM ; ; Dual Digital Potentiometer with EEPROM DS1867-10 ; ; Sets Stack bit to 0, Pot 1 to B0 (hex) and Pot 0 to 40H. ; ; copyright, Towanda Malone, Baltimore, MD, Sept, '98 LIST p=16f84 #include <p16f84.inc> __CONFIG 11h ; PIC DS1867 CONSTANT RST = 0 ; term 6 ----------------> term 5 CONSTANT CLK = 1 ; term 7 ----------------> term 6 CONSTANT DQ = 2 ; term 8 ----------------> term 8 CONSTANT BASE_VARS = 0CH ; starting point for variables STACK EQU BASE_VARS+0 R_POT_1 EQU BASE_VARS+1 R_POT_0 EQU BASE_VARS+2 O_BYTE EQU BASE_VARS+3 _N EQU BASE_VARS+4 ORG 000H BSF STATUS, RP0 ; RP1 = 0, RP0 = 1, BANK1 BSF TRISB, RST ; inputs BSF TRISB, CLK ; BSF TRISB, DQ ; BCF STATUS, RP0 ; bank 0 MAIN: MOVLW .0 ; dummy up some values MOVWF STACK MOVLW 0B0H MOVWF R_POT_1 MOVLW 40H MOVWF R_POT_0 CALL WRITE_VAL GOTO $ ; loop indefinitely WRITE_VAL: SSTART: BSF STATUS, RP0 BCF TRISB, DQ ; make these outputs BCF TRISB, CLK BCF TRISB, RST BCF STATUS, RP0 BCF PORTB, RST BCF PORTB, CLK BSF PORTB, RST ; bring RST high with CLK low OUT_STACK: BTFSC STACK, 0 ; ouput the stack bit and then clock BSF PORTB, DQ BTFSS STACK, 0 BCF PORTB, DQ CALL CLOCK_PULSE OUT_R_POT_1: ; output value for R_POT_1 MOVF R_POT_1, W MOVWF O_BYTE CALL OUT_BYTE OUT_R_POT_0: MOVF R_POT_0, W MOVWF O_BYTE CALL OUT_BYTE SSTOP: BCF PORTB, RST RETURN OUT_BYTE: ; output 8 bits, beginning with most sig bit MOVLW .8 MOVWF _N OUT_BYTE_1: RLF O_BYTE, F ; set the bit BTFSC STATUS, C BSF PORTB, DQ BTFSS STATUS, C BCF PORTB, DQ CALL CLOCK_PULSE ; and then clock DECFSZ _N, F GOTO OUT_BYTE_1 RETURN CLOCK_PULSE: BSF PORTB, CLK BCF PORTB, CLK RETURN END
' DS1867.BS2 ' ' Illustrates an interface with the BASIC Stamp 2 ' ' BASIC Stamp DS1867 ' ' P0, term 5 ----------------> (/RST), term 5 ' P1, term 6 ----------------> (CLK), term 6 ' P2, term 7 ----------------> (DQ), term 8 ' ' copyright, Towanda Malone, Baltimore, Sept, '98 ' STACK VAR BYTE R_POT_1 VAR BYTE R_POT_0 VAR BYTE O_BYTE VAR BYTE N VAR BYTE DIRS = $00 ' all inputs MAIN: STACK = 0 ' dummy up some values R_POT_1 = $B0 R_POT_0 = $40 GOSUB WRITE_VAL DONE: GOTO DONE WRITE_VAL: SSTART: DIR0 = 1 ' make /RST, CLK and DQ outputs DIR1 = 1 DIR2 = 1 OUT1 = 0 ' CLK low OUT0 = 1 ' /RST high OUT_STACK: OUT0 = STACK.BIT0 ' output the Stack bit GOSUB CLOCK_PULSE OUT_R_POT_1: O_BYTE = R_POT_1 GOSUB OUT_BYTE OUT_R_POT_0: O_BYTE = R_POT_0 GOSUB OUT_BYTE SSTOP: OUT0 = 0 ' bring /RST low RETURN OUT_BYTE: ' output 8 bits, beginning with most sig bit FOR N = 0 TO 7 OUT2 = O_BYTE.BIT7 GOSUB CLOCK_PULSE O_BYTE = O_BYTE * 2 ' shift one place to the left NEXT RETURN CLOCK_PULSE: ' bring CLK high and low OUT1=1 OUT1=0 RETURN
The 17 bits of wiper position data are not saved to EEPROM unless power
is lost. A minimum of
4 ms between 4.5 and 3.0 VDC is required on power down. This can easily
be achieved with a
0.1 uFd capacitor across the power terminals V_CC and GRD.
On power up, the data is automatically read from EEPROM. Note that
during the power up
recovery (a maximum of 10 msec) the pots are set to mid scale (80 hex).
Both the writing to and reading from EEPROM are transparent to the
The EEPROM "wear out" is specified at 50,000 writes.
Any number of DS1867 devices may be daisy chained on the same three
wire bus, with /RST and
CLK multipled to each device and C_OUT of the first DS1867 connected to DQ
of the second
and C_OUT of the second to DQ of the third, etc. This is simply a shift
For three devices where Device #3 is furthest from the processor;
/RST high Stack_3, Pot_1_3, Pot_0_3, Stack_2, Pot_1_2, Pot_0_2, Stack_1, Pot_1_0, Pot_0_1, /RST low
Note that in this case, 17 X 3 or 51 bits are sent.
Reading the Pot Settings.
The C_OUT terminal may also be used to read the content of a
potentiometer. Figure #5 in the
data sheet illustrates how C_OUT may be looped back to DQ through a series
A technique for reading the pot;
Configure processor terminal DQ as an input. /RST high
Note that C_OUT now may be read. A clock pulse causes the state on
C_OUT to be loaded into
the DQ input on the first DS1867.
This "read and clock" sequence is repeated 17 (or 34 or 51) times and
all bits are then back in
their previous positions. Bringing /RST low again engages the wipers.
Logic levels associated with the DS1867 are TTL levels; V_CC and
ground. An additional
terminal, V_B is provided to bias the substrate such that signals on the
potentiometer can range
from V_B to V_CC. For example, if V_B is tied to -5.0 VDC, the potentials
on the pot may
swing from -5.0 to 5.0 V.
It is worthy of note that the device may be clocked at anything from
near DC to 10 MHz. Each
pot setting requires 17 clock cycles and thus the resistance may be varied
This raises the possibility of using the DS1867 in real time feedback
control applications. In fact,
it might be used as a dual 8-bit digital to analog converter.
Again, note that the EEPROM write is performed only on power down, not
on each write to the
device. Thus, I assume the resistance could be changed some 500,000 times
However, I did not note this capability until we had completed testing and the fixture has since been taken down. Thus, this is somewhat speculative. I would be interested if anyone walks down this road.