This discussion deals with interfacing with an
The Ateml AT45DB321 is a 3.0 VDC device and thus in interfacing with a BX24 or similar processor having TTL (5V) logic outputs, it is neccessary to supply the EEPROM with 3.0 VDC, scale the levels on the /CS, SCK and Master Out Slave In (MOSI) from 5 Volt to 3 Volt logic and also boost the level of the Master In Slave Out from the EEPROM from 3 V to 5 V logic.
Rather than going through the agony of trying to find the AT45DB321,
mount this surface mount device and fool with these interface issues, we
opted for a
For some applications where the $99.00 cost is not a factor, the Rabbit board may be a viable path. It is a small standalone board which provides a connector and a number of through hole connector pads which we used for inserting wires to access +5 VDC, GRD, SCK, MOSI, MISO and /CS. The board includes a 3.0 VDC regulator and uses resistor dividers to scale the TTL to 3.0 VDC on SCK, MOSI and /CS. The boost from 3 to 5 VDC logic is implemented using a FET.
Note that this discussion is free. A similar discussion in interfacing with a PIC using C is not. Although we noted we were purchasing these units to develop this material for public distribution, Rabbit charged the full $200. Companies like to talk about education, but, all to often, talk is all it is.
There are some issues to consider if one is attempting to operate other SPI devices on the same bus (SCK, MOSI and MISO).
The scaling resistors associated with the /CS (series 1K, shunt 3.3K) will cause the EEPROM to be enabled when the /CS input is at a high impedance. This is an issue with the BX24 when using the hardware SPI interface as the BX24 boots with the general purpose IOs at a high impedance and thus, there is a situation where both the external EEPROM and the internal EEPROM associated with the BX24 are both enabled. This may be corrected by using a 1K pull-up to +5 VDC on the /CS input.
The boost on the MISO is implemented using a FET with the output being an open with a 1K pullup to +5 VDC when the EEPROM is idle. This is not quite the high impedance typically associated with the MISO lead. However, this shouldn't pose a problem in most cases as I assume other slave devices are capable of pulling the MISO to near ground through the 1K resistor. I might have gone for a 10K pullup, rather than expecting other slave devices to sink 5 mA.
The FET also has the effect of inverting the data on the MISO lead. That is, when reading, a logic one is interpretted as a zero, and a logic zero as a one. Thus, in the attached routines, you will note that Lisa performs a ones compliment on the read byte by exclusive oring with 0xff.