Regsiter and Bit Definitions for PIC16F84 (CCS PCM)


// DEFS_F84.H (CCS PCM)
//
// Definitions of file registers and bits.
//
// PIC16F84.  These agree with Microchip.
//
// Note that bits are lower case for C, upper case for assembly.
//
// copyright Peter H. Anderson, Scotland Co, NC, Mar, '99

// register definitions
#define W 0
#define F 1

// register files
#byte INDF          =0x00
#byte TMR0          =0x01
#byte PCL           =0x02
#byte STATUS        =0x03
#byte FSR           =0x04
#byte PORTA         =0x05
#byte PORTB         =0x06
#byte EEDATA        =0x08
#byte EEADR         =0x09
#byte PCLATH        =0x0a
#byte INTCON        =0x0b

#byte OPTION_REG    =0x81
#byte TRISA         =0x85
#byte TRISB         =0x86
#byte EECON1        =0x88
#byte EECON2        =0x89

#bit ra4	=0x05.4
#bit ra3	=0x05.3
#bit ra2	=0x05.2
#bit ra1	=0x05.1
#bit ra0	=0x05.0

#bit rb7	=0x06.7
#bit rb6	=0x06.6
#bit rb5	=0x06.5
#bit rb4	=0x06.4
#bit rb3	=0x06.3
#bit rb2	=0x06.2
#bit rb1	=0x06.1
#bit rb0	=0x06.0

#bit trisa4	=0x85.4
#bit trisa3	=0x85.3
#bit trisa2	=0x85.2
#bit trisa1	=0x85.1
#bit trisa0	=0x85.0

#bit trisb7	=0x86.7
#bit trisb6	=0x86.6
#bit trisb5	=0x86.5
#bit trisb4	=0x86.4
#bit trisb3	=0x86.3
#bit trisb2	=0x86.2
#bit trisb1	=0x86.1
#bit trisb0	=0x86.0


// INTCON Bits for C
#bit gie 	= 0x0b.7
#bit eeie	= 0x0b.6
#bit t0ie 	= 0x0b.5
#bit inte	= 0x0b.4
#bit rbie	= 0x0b.3
#bit t0if    	= 0x0b.2
#bit intf    	= 0x0b.1
#bit rbif     	= 0x0b.0

// OPTION Bits
#bit not_rbpu	= 0x81.7
#bit intedg     = 0x81.6
#bit t0cs       = 0x81.5
#bit t0se       = 0x81.4
#bit psa        = 0x81.3
#bit ps2        = 0x81.2
#bit ps1        = 0x81.1
#bit ps0        = 0x81.0

// EECON1 Bits
#bit eeif   	= 0x88.4
#bit wrerr  	= 0x88.3
#bit wren    	= 0x88.2
#bit wr      	= 0x88.1
#bit rd      	= 0x88.0


// For Assembly Language - Note upper case
// Status Bits
#define IRP 	7
#define RP1 	6
#define RP0 	5
#define NOT_TO 	4
#define NOT_PD 	3
#define Z 	2
#define DC 	1
#define C  	0

// INTCON Bits
#define GIE	7
#define EEIE    6
#define T0IE    5
#define INTE    4
#define RBIE    3
#define T0IF    2
#define INTF    1
#define RBIF    0

// OPTION Bits
#define NOT_RBPU	7
#define INTEDG          6
#define T0CS            5
#define T0SE            4
#define PSA             3
#define PS2             2
#define PS1             1
#define PS0             0

// EECON1 Bits

#define EEIF    4
#define WRERR   3
#define WREN    2
#define WR      1
#define RD      0